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f1977 datasheet 7bit, 75 , digital step attenuator 5 to 3000 mhz f1977, rev 1, 04/21/2016 1 ? 2016 integrated device technology, inc. g eneral d escription this document describes the specification for the f1977 digital step attenuator. the f1977 is part o f a family of glitchfree tm dsas optimized for the demanding requirements of catv and satellite systems. these devices are offered in a compact 5 mm x 5 mm 32 pin qfn package with 75 impedances for ease of integration. competitive advantage digital step attenuators are used in receivers and transmitters to provide gain control. the f1977 is a 7bit step attenuator optimized for these demanding applications. the silicon design has very low inse rtion loss, low distortion (+64 dbm iip3) and pinpoint attenuation accuracy. most importantly, the f1977 includes idts glitchfree tm technology which results in low overshoot & ringing during msb transitions. lowest insertion loss for best snr extremely accurate attenuation levels. ultra low distortion. glitchfree tm technology to protect pa or adc during transitions between attenuation states. applications ? catv infrastructure ? catv settop boxes ? catv satellite modems ? data network equipment ? fiber networks ordering information f eatures ? serial & 7 bit parallel interface ? 31.75 db control range ? 0.25 db step ? glitchfree tm for low transient overshoot ? low insertion loss: 1.4 db @ 1 ghz ? ultra linear iip3: +64 dbm ? attenuation error: 0.1 db @ 1 ghz ? stable attenuator accuracy over temperature ? bidirectional rf use ? 3.00 v to 5.25 v supply ? 1.8 v or 3.3 v control logic ? low current consumption: 325 a typical ? 40 c to +105 c operating temperature ? 5 mm x 5 mm thin qfn 32 pin package f unctional b lock d iagram glitch-free tm glitch-free tm F1977NBGI8 tape & reel green
f1977 7-bit, 75 ? , digital step attenuator 2 rev 1, 04/21/2016 a bsolute m aximum r atings parameter symbol min max units v dd to gnd v dd 0.3 +5.5 v d[6:0], data, clk, le, a0, a1, a2, v mode v cntl 0.3 minimum (v dd + 0.3, 3.9) v dc voltage rf1, rf2 v rf 0.3 +0.3 v maximum input power applied to rf1 or rf2 (>100 mhz) p rf +34 dbm maximum junction temperature t j max +150 c storage temperature range t st 65 +150 c lead temperature (soldering, 10 s) t lead +260 c electrostatic discharge C hbm (jedec/esda js0012012) v esdhbm 1000 (class 1c) v esd voltage C cdm (per jesd22c101f) v esdcdm 500 (class c2) v stresses above those listed above may cause permane nt damage to the device. functional operation of th e device at these or any other conditions above those indicated in the operational section of this specification i s not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd c aution this product features proprietary protection circui try. however, it may be damaged if subjected to hi gh energy esd. please use proper esd precautions when handling to avoid damage or loss of performance. p ackage t hermal and m oisture c haracteristics ja (junction C ambient) 40 c/w jc (junction C case) [the case is defined as the expo sed paddle] 4 c/w moisture sensitivity rating (per jstd02 msl1
f1977 rev 1, 04/21/2016 3 7-bit, 75 ? , digital step attenuator f1977 r ecommended o perating c onditions parameter symbol conditions min typ max units supply voltage v dd 3 5.25 v frequency range f rf 5 3000 mhz operating temperature range t case exposed paddle 40 105 c rf cw input power p cw rf1 or rf2 see figure 1 dbm rf1 impedance z rf1 single ended 75 rf2 impedance z rf2 single ended 75 figure 1 - maximum continuous operating rf input power versus input frequency 0 4 8 12 16 20 24 28 32 0.01 0.10 1.00 10.00 100.00 1000.00 max cw p in (dbm) frequency (mhz)
f1977 7-bit, 75 ? , digital step attenuator 4 rev 1, 04/21/2016 f1977 s pecification specifications apply at v dd = +3.3 v, t case = +25c, f rf = 1 ghz, pin = 10 dbm unless otherwise noted. se rial mode. z rf1 = z rf2 = 75 . evkit losses are deembedded unless otherwise no ted. parameter symbol conditions min typ max units logic input high v ih clk, le, data, d[6:0], a0, a1, a2, v mode v dd > 3.6 v 1.17 1 3.6 v 3.0 v dd 3.6 1.17 v dd logic input low v il clk, le, data, d[6:0], a0, a1, a2, v mode 0.63 v logic current i ih, i il individual pins -40 +40 a supply current i dd v dd = 3.3 v 322 365 a v dd = 5.0 v 375 attenuation range att rng 31.75 db minimum gain step lsb monotonic for f rf 3 ghz 0.25 db insertion loss il f rf = 1 ghz 1.4 1.9 db f rf = 2 ghz to 3 ghz 2.2 relative insertion phase (a min vs. a max ) ? f rf = 1 ghz 18 deg f rf = 2 ghz 36 step error (differential nonlinearity) dnl max error between adjacent steps 0.10 db absolute attenuation error (integral nonlinearity) inl max error for state 19.75 db, f rf = 1 ghz -0.4 0.1 +0.5 db max error, over all states f rf = 1 ghz 0.8 +0.5 input return loss s11 5 mhz f rf 1.5 ghz 18 db 1.5 ghz < f rf 3.0 ghz 15 output return loss s22 5 mhz f rf 1.5 ghz 17 db 1.5 ghz < f rf 3.0 ghz 15 specification notes: note 1: items in min/max columns in bold italics are guaranteed by test. note 2: items in min/max columns that are not bold/ italics are guaranteed by design characterization. note 3. the input 0.1db compression point is used a s a linearity figure of merit. the recommended max imum input power is specified as the lesser of the two values from figure 1 and figure 2 above. note 4: spurious due to onchip negative voltage ge nerator. typical generator fundamental frequency i s 2.2 mhz. note 5: minimum time required between switching of attenuations states = 1 / (maximum switching rate).
f1977 rev 1, 04/21/2016 5 7-bit, 75 ? , digital step attenuator f1977 s pecification specifications apply at v dd = +3.3 v, t case = +25c, f rf = 1 ghz, pin = 10 dbm unless otherwise noted. se rial mode. z rf1 = z rf2 = 75 . evkit losses are deembedded unless otherwise no ted. parameter symbol conditions min typ max units input ip3 iip3 p in = +10 dbm per tone 50 mhz tone separation attn state = 0.00 db 64 dbm attn state = 15.75 db 64 attn state = 31.75 db 64 input 0.1db compression 3 p 0.1db f rf = 1 ghz attn = 10 db measured in 50 ohms 32 dbm dsa settling time set max to min attenuation to settle to within 0.5 db of final value 0.9 s min to max attenuation to settle to within 0.5 db of final value 1.8 video feedthrough rf1, rf2 ports vid ft measured at rf ports with 2.5 ns risetime, 0 to 3.3 v control pulse 10 mv pp maximum spurious level on any rf port 4 spur max spur freq ~ 2.2 mhz 119 dbm serial clock speed f clk spi 3 wire bus 25 mhz parallel to serial setup a spi 3 wire bus 100 ns serial data hold time b spi 3 wire bus 10 ns le delay c spi 3 wire bus time from final serial clock rising edge 10 ns maximum switching rate 5 sw rate 25 khz specification notes: note 1: items in min/max columns in bold italics are guaranteed by test. note 2: items in min/max columns that are not bold/ italics are guaranteed by design characterization. note 3. the input 0.1db compression point is used a s a linearity figure of merit. the recommended max imum input power is specified as the lesser of the two values from figure 1 and figure 2 above. note 4: spurious due to onchip negative voltage ge nerator. typical generator fundamental frequency i s 2.2 mhz. note 5: minimum time required between switching of attenuations states = 1 / (maximum switching rate).
f1977 7-bit, 75 ? , digital step attenuator 6 rev 1, 04/21/2016 p rogramming o ptions f1977 can be programmed using either the parallel o r serial interface; selectable via v mode (pin 3). serial mode is selected by floating v mode or pulling v mode to a logic high and parallel mode is selected by s etting v mode to logic low. s erial c ontrol m ode f1977 serial mode is selected by floating v mode (pin 3) or pulling it to logic high. the serial i nterface is a 16bit shift register made up of two words. the fi rst 8bit word is the attenuation word, which contr ols the dsa state. the second word is the address word, wh ich uses only 3 of 8bits that must match the hard wired a0a2 programming in order to change the dsa state. if no external connections are made to a0 C a2 th en internally they will default to 000 due to internal pull down resistors. if these 3 external preset a ddress bits are not matched with the spi loaded address bits th en the current attenuator state will remain unchang ed. this allows up to 8 serialcontrolled devices to be used on a single board, which share a common data, clk and le. when serial programming is used, all the parallel c ontrol input pins 26 C 32 can be left open or groun ded. if a pin is grounded than an additional 25 a will be dr awn from the voltage supply per pin. set to either logic high or low set to logic low msb (last in) lsb (first in) q15 q14 q13 q12 q11 q10 q9 q8 q7 q6 q5 q4 q3 q2 q1 q0 a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 8bit address word 8bit attenuation word figure 2 - two 8-bit words are comprised of 16-bit seria l in, parallel out shift register table 1 - truth table for the serial address word a7 (msb) a6 a5 a4 a3 a2 a1 a0 address setting x x x x x 0 0 0 000 x x x x x 0 0 1 001 x x x x x 0 1 0 010 x x x x x 0 1 1 011 x x x x x 1 0 0 100 x x x x x 1 0 1 101 x x x x x 1 1 0 110 x x x x x 1 1 1 111
f1977 rev 1, 04/21/2016 7 7-bit, 75 ? , digital step attenuator table 2 - truth table for the serial control word d7 d6 d5 d4 d3 d2 d1 d0 (lsb) attenuation state (db) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0.25 0 0 0 0 0 0 1 0 0.5 0 0 0 0 0 1 0 0 1 0 0 0 0 1 0 0 0 2 0 0 0 1 0 0 0 0 4 0 0 1 0 0 0 0 0 8 0 1 0 0 0 0 0 0 16 0 1 1 1 1 1 1 1 31.75 s erial m ode d efault c ondition when the device is first powered up it will default to the maximum attenuation setting as described below: note that for the f1977 in all cases logic high (1) = attenuation stepped in, while logic low (0) = at tenuation stepped out. msb (last in) lsb (first in) q15 q14 q13 q12 q11 q10 q9 q8 q7 q6 q5 q4 q3 q2 q1 q0 a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 x x x x x 0 0 0 0 1 1 1 1 1 1 1 8bit address word 8bit attenuation word figure 3 -default register settings set for max att enuation and 000 address word r egister t iming d iagram : (n ote the t iming s pec i ntervals in b lue ) with serial control, the f1977 can be programmed vi a the serial port on the rising edge of latch enabl e (le) which loads the last 8 data line bits [formatted ls b (d0) first] resident in the shift register follow ed by the address word into the active register.
f1977 7-bit, 75 ? , digital step attenuator 8 rev 1, 04/21/2016 v mode t p 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 clk spec t ps t dht t ds t cls interval t dst t lew le data d0 d1 d2 d3 d4 d5 d6 d7 a0 a1 a2 a3 a4 a5 a6 a7 0.25 db 0.5 db 2 db 2 db 4 db 8 db 16 db low bit 1 b it 2 bit 3 bit 4 dc dc dc dc lsb msb lsb msb time data word latched into the active register figure 4 - serial timing diagram note when latch enable (le) is high, the shift re gister is disabled and data is not continuously clo cked into the shift register which minimizes noise. it is recommended that latch enable be left high when the device is not being programmed. table 3 - serial mode timing table interval symbol description min spec max spec units t ps parallel to serial setup time from rising edge of vmode to rising edge of clk for d5 100 ns t p clock high pulse width 10 ns t cls le setup time from the rising edge of clk pulse for d0 to le rising edge minus half the clock period. 10 ns t lew le pulse width 30 ns t dst data setup time from the starting edge of data bit to rising edge of clk 10 ns t dht data hold time from rising edge of clk to falling edge of the data bit. 10 ns p arallel c ontrol m ode for the f1977 the user has the option of running in one of two parallel modes. direct parallel mode o r latched parallel mode. direct parallel mode: direct parallel mode is selected when v mode is a logic low and le is a logic high. in this mo de the device will immediately react to any voltage changes to the par allel control pins [pins 26 C 32]. use direct para llel mode for the fastest settling time.
rev 1, 04/21/2016 latched parallel mode: latched parallel mode is selected when v latched parallel mode: ? set v mode is logic low. ? set le to logic low. ? adjust pins [26, 27, 28, 29, 30, 31, 32] to the des ired attenuation setting. low, the attenuation state will not change. ? pull le to a logic high. the device will then transition to the attenuation settings reflected by pins d6 d0. latched parallel default startup condition: latched parallel mode implies a default state for w hen the device is first powered up with v low and le logic low . in this case the default setting is maximum atte nuation. table 4 - truth table for the parallel control word d6 d5 d4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 0 1 1 1 figure 5 - 9 7- bit, 75 latched parallel mode is selected when v mode is logic low and le is toggled from logic low to h adjust pins [26, 27, 28, 29, 30, 31, 32] to the des ired attenuation setting. ( w low, the attenuation state will not change. ) the device will then transition to the attenuation settings reflected by pins latched parallel default startup condition: latched parallel mode implies a default state for w hen the device is first powered up with v . in this case the default setting is maximum atte nuation. truth table for the parallel control word d3 d2 d1 d0 attenuation (db) 0 0 0 0 0 0 0 1 0 0 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 31.75 - latched parallel mode timing diagram f1977 75 ? , digital step attenuator logic low to h igh. to utilize w hile le is set to a logic the device will then transition to the attenuation settings reflected by pins latched parallel mode implies a default state for w hen the device is first powered up with v mode set for logic attenuation (db) 0 0.25 0.5 1 2 4 8 16 31.75
f1977 7-bit, 75 ? , digital step attenuator 10 rev 1, 04/21/2016 table 5 - latched parallel mode timing interval symbol description min spec max spec units t sps serial to parallel mode setup time 100 ns t pdh parallel data hold time 10 ns t le le minimum pulse width 10 ns t pds parallel data setup time 10 ns t ypical o perating c onditions (toc) unless otherwise noted for the toc graphs on the fo llowing pages, the following conditions apply. ? v dd = +3.30 v ? t case = +25 c ? p in = 0 dbm for single tone measurements ? p in = +15 dbm/tone for multi-tone measurements ? 50 mhz tone space ? serial control ? rf1 port is the input port ? attenuation setting = 0 db ? measured in a 75 ohm system ? evkit losses (traces and connectors) are fully de-embe dded
f1977 rev 1, 04/21/2016 11 7-bit, 75 ? , digital step attenuator t ypical o perating c onditions (- 1 -) insertion loss vs frequency rf1 return loss vs frequency [all states] rf2 return loss vs frequency [all states] insertion loss vs attenuation state rf1 return loss vs attenuation state rf2 return loss vs attenuation state -3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 insertion loss (db) frequency (ghz) -40 c +25 c +105 c -40 -35 -30 -25 -20 -15 -10 -5 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 match (db) frequency (ghz) -40 -35 -30 -25 -20 -15 -10 -5 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 match (db) frequency (ghz) -35 -30 -25 -20 -15 -10 -5 0 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 insertion loss (db) attenuation (db) 1 ghz, -40 c 1 ghz, +25 c 1 ghz, +105 c -40 -35 -30 -25 -20 -15 -10 -5 0 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 match(db) attenuation (db) 0.01 ghz 0.25 ghz 0.50 ghz 0.75 ghz 1.00 ghz 1.25 ghz 1.50 ghz 1.75 ghz 2.00 ghz 2.25 ghz 2.50 ghz 2.75 ghz -40 -35 -30 -25 -20 -15 -10 -5 0 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 match (db) attenuation (db) 0.01 ghz 0.25 ghz 0.50 ghz 0.75 ghz 1.00 ghz 1.25 ghz 1.50 ghz 1.75 ghz 2.00 ghz 2.25 ghz 2.50 ghz 2.75 ghz
f1977 7-bit, 75 ? , digital step attenuator 12 rev 1, 04/21/2016 t ypical o perating c onditions (- 2 -) relative insertion phase vs frequency worst case absolute accuracy vs frequency worst case step accuracy vs frequency relative insertion phase vs attenuation absolute accuracy vs attenuation step accuracy vs attenuation -5 0 5 10 15 20 25 30 35 40 45 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 phase (degrees) frequency (ghz) -1.2 -1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 error (db) frequency (ghz) -40 c min -40 c max +25 c min +25 c max +105 c min +105 c max -0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 error (db) frequency (ghz) -40 c min -40 c max +25 c min +25 c max +105 c min +105 c max -5 0 5 10 15 20 25 30 35 40 45 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 phase (degrees) attenuation (db) 0.01 ghz 0.25 ghz 0.50 ghz 0.75 ghz 1.00 ghz 1.25 ghz 1.50 ghz 1.75 ghz 2.00 ghz 2.25 ghz 2.50 ghz 2.75 ghz -1.2 -1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 error (db) attenuation (db) 0.01 ghz 0.25 ghz 0.50 ghz 0.75 ghz 1.00 ghz 1.25 ghz 1.50 ghz 1.75 ghz 2.00 ghz 2.25 ghz 2.50 ghz 2.75 ghz -0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 error (db) attenuation (db) 0.01 ghz 0.25 ghz 0.50 ghz 0.75 ghz 1.00 ghz 1.25 ghz 1.50 ghz 1.75 ghz 2.00 ghz 2.25 ghz 2.50 ghz 2.75 ghz
f1977 rev 1, 04/21/2016 13 7-bit, 75 ? , digital step attenuator t ypical o perating c onditions (- 3 -) input compression at 50 mhz input compression 1.0 ghz input compression 2.0 ghz input compression 500 mhz input compression 1.5 ghz input ip3 -0.5 -0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 0.5 16 18 20 22 24 26 28 30 32 34 compression (db) input power (dbm) 0.00 db 1.00 db 2.00 db 4.00 db measured in a 50 ohm system -0.5 -0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 0.5 16 18 20 22 24 26 28 30 32 34 compression (db) input power (dbm) 0.00 db 1.00 db 2.00 db 4.00 db measured in a 50 ohm system -0.5 -0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 0.5 16 18 20 22 24 26 28 30 32 34 compression (db) input power (dbm) 0.00 db 1.00 db 2.00 db 4.00 db measured in a 50 ohm system -0.5 -0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 0.5 16 18 20 22 24 26 28 30 32 34 compression (db) input power (dbm) 0.00 db 1.00 db 2.00 db 4.00 db measured in a 50 ohm system -0.5 -0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 0.5 16 18 20 22 24 26 28 30 32 34 compression (db) input power (dbm) 0.00 db 1.00 db 2.00 db 4.00 db measured in a 50 ohm system 40 45 50 55 60 65 70 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 input ip3 (dbm) frequency (ghz) 0.00 db 0.50 db 1.00 db 2.00 db 4.00 db 6.00 db 12.00 db 18.00 db 24.00 db 31.50 db
f1977 7-bit, 75 ? , digital step attenuator 14 rev 1, 04/21/2016 p ackage d rawing (5 mm x 5 mm 32pin tqfn), use exposed pad (epad) option p1
f1977 rev 1, 04/21/2016 15 7-bit, 75 ? , digital step attenuator l and p attern d imension p in d iagram exposed pad (gnd) 1 2 3 4 5 6 7 8 dnc v dd v mode a0 gnd gnd rf1 gnd clk le a1 a2 nc gnd rf2 gnd gnd gnd gnd gnd gnd gnd gnd gnd d0 d1 d2 d3 d4 d5 d6 data 25 26 27 28 29 30 31 32 9 10 11 12 13 14 15 16 24 23 22 21 20 19 18 17 top view (looking through the top of the package)
f1977 7-bit, 75 ? , digital step attenuator 16 rev 1, 04/21/2016 p in d escription pin name function 1 dnc this pin must be left open. 2 v dd main supply. use 3.3 v or 5 v. bypass capacitor a s close to pin as possible. 3 v mode 1 logic low for parallel mode. logic high or nc for serial mode. 4 a0 2 address bit a0 connection. 5 gnd connect directly to paddle ground or as close as po ssible to pin with thru via. this pin is not internally connected. 6 gnd connect directly to paddle ground or as close as po ssible to pin with thru via. 7 rf1 3 device rf input or output (bidirectional). 8 C 17 gnd connect each pin directly to paddle ground or as cl ose as possible to pin with thru vias. 18 rf2 3 device rf input or output (bidirectional). 19 gnd connect directly to paddle ground or as close as po ssible to pin with thru via. 20 nc no internal connection. these pins can be left unco nnected, voltage applied, or connected to ground (recommended). 21 a2 2 address bit a2 connection 22 a1 2 address bit a1 connection. 23 le 1 serial interface latch enable input. 24 clk 1 serial interface clock input. 25 data 1 serial interface data input. 26 d6 1 parallel control bit, 16 db. 27 d5 1 parallel control bit, 8 db. 28 d4 1 parallel control bit, 4 db. 29 d3 1 parallel control bit, 2 db. 30 d2 1 parallel control bit, 1 db. 31 d1 1 parallel control bit, 0.5 db. 32 d0 1 parallel control bit, 0.25 db. ep exposed paddle connect to ground with multiple vias for good therm al and rf performance. pin description notes: note 1: includes an internal 100 k? pullup resisto r to an internal regulated 2.5v supply. if pin is grounded then there is an additional 25 a per pin for the supply current. note 2: includes an internal 100 k? pulldown resi stor to gnd. note 3: rf pins 7 and 18 do not require dc blockin g capacitors for operation if they are at 0 v dc. if they are not at 0v dc, then they require dc blocking capacitors.
f1977 rev 1, 04/21/2016 17 7-bit, 75 ? , digital step attenuator e v k it p icture
f1977 7-bit, 75 ? , digital step attenuator 18 rev 1, 04/21/2016 ev kit / a pplications c ircuit
f1977 rev 1, 04/21/2016 19 7-bit, 75 ? , digital step attenuator evk it bom item # part reference qty description mfr. part # mfr. 1 c1, c11, c15 3 100 nf 10%, 16 v, x7r ceramic capacitor (0402) grm155r71c104k murata 2 c2, c10 2 10 nf 5%, 50 v, x7r ceramic capacitor (0603) grm188r71h103j murata 3 c3 c9, c12, c13, c14, c31 c34 14 100 pf 5%, 50 v, c0g ceramic capacitor (0402) grm1555c1h101j murata 4 r3 r9, r31 r34 11 100 1%, 1/10w, resistor (0402) erj2rkf1000x panasonic 5 r10 r13, r15r18, r24r30, r35, r36 17 0 resistors (0402) erj2ge0r00x panasonic 6 r21, r22, r23 3 3 k 1%, 1/10w, resistor (0402) erj 2rkf3001x panasonic 7 r1 1 8.2 k 1%, 1/10w, resistor (0402) erj 2rkf8201x panasonic 8 r2 1 10 k 1%, 1/10w, resistor (0402) erj 2rkf1002x panasonic 9 j2, j3, j5 3 conn header vert sgl 2 x 1 pos gold 961102 6404 ar 3m 10 j14, j15 1 conn header vert dbl 4 x 2 pos gold 67997 108hlf fci 11 j4 1 conn header vert sgl 12 x 1 pos gold 961112 6404 ar 3m 12 j1, j8 2 edge launch sma (0.250 inch pitch ground, round) 1420711821 emerson johnson 13 j6, j7 2 edge launch f type 75 ohm sma 222181 amphenol 14 u2 1 switch 10 position dip switch kat1110e e switch 15 u1 1 dsa f1977ncgi idt 16 1 printed circuit board f1977 evkit rev 01 idt t op m arkings idt f1977nbgi z1535g part number date code [yyww] (week 35 of 2015) asm test step assembler code q61a003my lot code
f1977 7-bit, 75 ? , digital step attenuator 20 rev 1, 04/21/2016 a pplications i nformation power supplies a common vcc power supply should be used for all pi ns requiring dc power. all supply pins should be bypassed with external capacitors to minimize noise and fast transients. supply noise can degrade nois e figure and fast transients can trigger esd clamps and caus e them to fail. supply voltage change or transients should have a slew rate smaller than 1 v / 20 s. in addi tion, all control pins should remain at 0 v (+/0.3 v) while the supply voltage ramps or while it returns to zer o. digital pin voltage & resistance values the following table provides opencircuit dc voltag e referenced to ground and resistance values for ea ch of the control pins listed. pin name open circuit dc voltage internal connection 3 v mode 2.5 v 100 k? pullup resistor to internally regulated 2.5 v 4, 21, 22 a0, a2, a1 0 v 100 k? resistor to gnd 23, 24, 25 le, clk, data 2.5 v 100 k? pullup resistor to internally regulated 2.5 v 2632 d[6:0] 2.5 v 100 k? pullup resistor to internally regulated 2.5 v
f1977 corporate headquarters 6024 silver creek valley road san jose, ca 95138 usa sales 1-800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com tech support www.idt.com/go/support disclaimer integrated device technology, inc. (idt) reserves the right to modify the products and/or sp ecifications described herein at any time, without notice, at idt's sole discretion. performance specifications and operating parameters of the described products are determined in an ind ependent state and are not guaranteed to perform th e same way when installed in customer products. the information contained herein is provi ded without representation or warranty of any kind, whether express or implied, including, but not lim ited to, the suitability of idt's products for any particular purpose, an implied warranty of merc hantability, or noninfringement of the intellectua l property rights of others. this document is pres ented only as a guide and does not convey any license under intellectual property rights of idt o r any third parties. idt's products are not intended for use in applicat ions involving extreme environmental conditions or in life support systems or similar devices where th e failure or malfunction of an idt product can be reasonably expected to significantly affect the health or safety of users. anyone using an idt pro duct in such a manner does so at their own risk, ab sent an express, written agreement by idt. integrated device technology, idt and the idt logo are trademarks or registered trademarks of idt and its subsidiaries in the united states and other cou ntries. other trademarks used herein are the property of idt or their respective third party owners. copyright ?2016 integrated device technology, inc.. all rights reserved. rev 1, 04/21/2016 21 7-bit, 75 ? , digital step attenuator r evision h istory s heet rev date page description of change o 2016feb19 initial release 1 2016apr21 2 typo on v hbm rating. voltage changed from 1.5kv to 1kv. no chn g. to class

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